library ieee;
use ieee.std_logic_1164.all;

entity mips_test_bench is
end entity;

architecture arch_test_bench of mips_test_bench is
    component mips is
		port (	dump, rst, clk : in std_logic;
				pc, instr : out std_logic_vector(31 downto 0));
    end component;
    
    signal clk_test, rst_test, dump_test : std_logic;
    signal pc_test, instr_test : std_logic_vector(31 downto 0);
    
    begin
        wdf: mips port map (clk => clk_test, rst => rst_test, dump => dump_test, pc => pc_test, instr => instr_test);
        process begin
			clk_test <= '0';
			wait for 5 ns;
			clk_test <= '1';
			wait for 5 ns;
        end process;
        
        process begin
        	rst_test <= '1';
        	dump_test <= '0';
        	wait for 20 ns;
        	rst_test <= '0';
        	wait for 170 ns;
        	dump_test <= '1';
        	wait for 30 ns;
        end process;
end architecture;
